1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit (IC) devices and, more particularly, to a semiconductor IC chip with bond pad structures formed over a circuit region.
2. Description of the Prior Art
Performance characteristics of semiconductor devices are typically improved by reducing device dimensions, resulting in increased device densities and increased device packaging densities. This increase in device density places increased requirements on the interconnection of semiconductor devices, which are addressed by the packaging of semiconductor devices. One of the key considerations in the package design is the accessibility of the semiconductor device or the Input/Output (I/O) capability of the package after one or more devices have been mounted in the package.
In a typical semiconductor device package, the semiconductor die can be mounted or positioned in the package and can further be connected to interconnect lines of the substrate by bond wires or solder bumps. For this purpose the semiconductor die is provided with bond pads that are typically mounted around the periphery of the die and not formed over regions containing active or passive devices. FIG. 1 is schematic plan view showing a conventional layout of bond pads over a semiconductor die. In FIG. 1, a semiconductor die 10 is provided with a first region 12 in which active and/or passive devices (not shown) are formed. The first region 12 is separated from a second region 14, over which bond pads 16 are formed.
One reason the bond pads 16 are not formed over the first region 12 is related to the thermal and/or mechanical stresses that occur during the conductive bonding process. During conductive bonding, wires or bumps are connected from the bond pads to a supporting circuit board or to other means of interconnections.
Therefore, materials for intermetal dielectrics (not shown) incorporated in a interconnect structure of the semiconductor die 10, typically adjacent to and/or underlying the bond pads 16, are susceptible to damage during the conductive bonding due to insufficient mechanical strength against the bonding stresses. Thus, direct damage to the active or passive devices underlying the intermetal dielectric layers can be avoided since bond pads are provided around the periphery of the die. In such a design, however, overall die size cannot be significantly reduced since the bond pads 16 occupy a large portion of the top surface of the semiconductor die 10, causing extra manufacturing cost.